°°ħħ²² Cyrix Cx486SLC/DLC ²²ħħ°° ************************** PART I. - UTILITIES ****************************** Using the Cx486SLC/DLC Utilities ---------------------------------------------------------------------------- This disk should contain the following files in the root directory m5b.exe interactive cache control utility m5b.cfg default cache settings .cfg file m5_det.exe detects the Cx486SLC/DLC microprocessor dma_tst.exe checks the dma cache coherency a20m_tst.exe checks the a20m# hw modifications DETECTING the Cx486SLC/DLC ---------------------------------------------------------------------------- To detect the Cx486SLC/DLC: m5_det.exe VIEWING the STATUS of the Cx486SLC/DLC CACHE REGISTERS ---------------------------------------------------------------------------- To VIEW the Cx486SLC/DLC cache registers type: m5b.exe (set the path appropriately) INTERACTIVELY CONTROLLING the Cx486SLC/DLC INTERNAL CACHE with M5B.EXE --------------------------------------------------------------------------- To use the M5.EXE utility from the command line type: m5b.exe (set the path appropriately) To automatically turn on the cache during boot using the M5B.CFG file add the following line to the AUTOEXEC.BAT file: m5b q m5b.cfg (set the path appropriately) NOTE: The "user input starting address" for the Non-Cacheable Regions (NCR) should fall on a boundary that coincides with the size of the Non-Cacheable Region. M5B.EXE automatically translates the user's starting address to the "effective starting address" calculated by the Cx486SLC/DLC. Example 1 (correct): To set 640k to 1M as Non-Cacheable: NCR1 start address: A0000 size: 128k (A0000 is on 128k boundary) NCR2 start address: C0000 size: 256k (C0000 is on 256k boundary) Example 2 (correct): To set 512k to 1M as Non-Cacheable: NCR1 start address: 80000 size: 512k (80000 is on 512k boundary) *********************************************************************** M5B.CFG This file is used by the program M5B.EXE to configure the cache registers according to the data contained in the file. M5B.EXE reads each line in this file looking for a matching token(setup string) so it can convert the string into the value for the appropriate register. To use this file, look for the token(setup string) lines at the end of each section below. Enter a HEX value that appropriately sets up the cache. You can edit the value on the right side of the "=" sign, but you cannot edit the token itself. *********************************************************************** Cache Configuration Register 0 Register 0C0h Bit 0 - NC0: If = 1, sets the first 64K bytes at each 1M byte boundry as non-cacheable, when operating in real or virtual 8086 mode. 1 - NC1: If = 1, sets the 640K to 1M region as non- cacheable. 2 - A20M: If = 1, enables A20M# input pin. 3 - KEN: If = 1, enables KEN# input pin. 4 - FLUSH: If = 1, enables KEN# input pin. 5 - BARB: If =, enables flushing of internal cache when hold state is entered. 6 - C0: Selects cache organization: 0 = 2-way set associative 1 = directed mapped 7 - SUSPEND: If = 1, enables SUSP# input and SUSPA# output pins. setup string (value in HEX) CC_0=1 *********************************************************************** Cache Configuration Register 1 Register 0C1h Bit 0 - RPL: If = 1, enables output pins RPLSET and RPLVAL#. If not enabled, outputs RPLSET and RPLVAL# wil float. setup string (value in HEX) CC_1=0 *********************************************************************** Non-Cacheable Region Sizes: For Reference: 0 = Disabled 1 = 4 Kbytes 2 = 8 Kbytes 3 = 16 Kbytes 4 = 32 Kbytes 5 = 64 Kbytes 6 = 128 Kbytes 7 = 256 Kbytes 8 = 512 Kbytes 9 = 1 Mbytes 0Ah = 2 Mbytes 0Bh = 4 Mbytes 0Ch = 8 Mbytes 0Dh = 16 Mbytes 0Eh = 32 Mbytes 0Fh = 4 Gbytes *********************************************************************** Non-Cacheable Region 1 Register C4, C5, and C6 C4h Bits 7-0 - Address bits A31 - A24 of Region 1 starting address C5h Bits 7-0 - Address bits A23 - A16 of Region 1 starting address C6h Bits 7-4 - Address bits A15 - A12 of Region 1 starting address 3-0 - Size of non-cacheable Region 1 setup strings (values in HEX) NCR_1_C4=00 NCR_1_C5=0a NCR_1_C6=06 *********************************************************************** Non-Cacheable Region 2 Register C7, C8 and C9h C7h Bits 7-0 - Address bits A31 - A24 of Region 2 starting address C8h Bits 7-0 - Address bits A23 - A16 of Region 2 starting address C9h Bits 7-4 - Address bits A15 - A12 of Region 2 starting address 3-0 - Size of non-cacheable Region 2 setup strings (values in HEX) NCR_2_C7=00 NCR_2_C8=0c NCR_2_C9=07 *********************************************************************** Non-Cacheable Region 3 Register CA, CB and CCh CAh Bits 7-0 - Address bits A31 - A24 of Region 3 starting address CBh Bits 7-0 - Address bits A23 - A16 of Region 3 starting address CCh Bits 7-4 - Address bits A15 - A12 of Region 3 starting address 3-0 - Size of non-cacheable Region 3 setup strings (values in HEX) NCR_3_CA=00 NCR_3_CB=00 NCR_3_CC=00 *********************************************************************** Non-Cacheable Region 4 Register CD, CE and CFh CDh Bits 7-0 - Address bits A31 - A24 of Region 4 starting address CEh Bits 7-0 - Address bits A23 - A16 of Region 4 starting address CFh Bits 7-4 - Address bits A15 - A12 of Region 4 starting address 3-0 - Size of non-cacheable Region 4 setup strings (values in HEX) NCR_4_CD=00 NCR_4_CE=00 NCR_4_CF=00 ******************** PART II. - PROGRAMMING EXAMPLES ********************* The programming examples supplied on this disk are ASSEMBLY language routines. MAKE files are provided with debugging switches enabled for your reference. Each example is under its respective directory. TURNING ON the Cx486SLC/DLC INTERNAL CACHE - Example ---------------------------------------------------------------------------- do_cache.asm - example to enable the internal cache registers with a 640k to 1M non-cacheable region. TURNING OFF the Cx486SLC/DLC INTERNAL CACHE - Example ---------------------------------------------------------------------------- no_cache.asm - example to return to internal cache registers to the reset state. DETECTING the Cx486SLC/DLC ---------------------------------------------------------------------------- m5_det.c - driver program for detect.asm detect.asm - example to detect the Cx486SLC/DLC using the undefined arithmatic flags after a divide instruction. M5B.EXE REVSION STATUS: ---------------------------- rev 1.0 - new ----------------------------