/**** drreg.h ****/ /* registers and defines for DRQ-3b. Wish us luck!!!*/ /* dma registers for DRQ-3B */ struct drdevice { u_short data_window; /* data window register */ short address_window; /* address window register */ u_short port_config; /* port configuration register */ short port0_data; /* port 0 data register */ short port1_data; /* port 1 data register */ short transfer_count; /* transfer_count register */ u_short function; /* function register */ u_short status; /* status register */ }; struct chain { /* chain control block, will only use */ short control; /* first 3 words, but better allocate */ short word1; /* whole thing anyway */ short word2; short word3; short word4; short word5; short word6; short word7; short word8; short word9; short word10; short word11; short word12; short word13; short word14; short word15; short word16; } chain; # define bit(x) ((1) << (x)) #define DMAput(reg,data) \ draddr->address_window = reg; \ draddr->data_window = data #define DMAor(reg,data) \ draddr->address_window = reg; \ draddr->data_window |= data #define DMAand(reg,data) \ draddr->address_window = reg; \ draddr->data_window &= data #define DMAprint(reg) \ draddr->address_window = reg; \ printf("reg = %o\n",draddr->data_window) /* DMA registers, addressed through data_window and address_window */ #define CH_MODE_HI_0 0126 #define CH_MODE_HI_1 0124 #define CH_MODE_LO_0 0122 #define CH_MODE_LO_1 0120 #define MASK_0 0116 #define MASK_1 0114 #define PATTERN_0 0112 #define PATTERN_1 0110 #define MASTERMODE 070 #define BASE_OP_COUNT_0 066 #define BASE_OP_COUNT_1 064 #define CUR_OP_COUNT_0 062 #define CUR_OP_COUNT_1 060 #define DMA_STATUS_0 056 #define DMA_STATUS_1 054 #define COMMAND_0 056 #define COMMAND_1 054 #define INT_SAVE_0 052 #define INT_SAVE_1 050 #define CHAIN_ADDR_SEG_0 046 #define CHAIN_ADDR_SEG_1 044 #define CHAIN_ADDR_OFF_0 042 #define CHAIN_ADDR_OFF_1 040 #define BASE_ADDR_SEG_A_0 036 #define BASE_ADDR_SEG_A_1 034 #define CUR_ADDR_SEG_A_0 032 #define CUR_ADDR_SEG_A_1 030 #define BASE_ADDR_SEG_B_0 026 #define BASE_ADDR_SEG_B_1 024 #define CUR_ADDR_SEG_B_0 022 #define CUR_ADDR_SEG_B_1 020 #define BASE_ADDR_OFF_A_0 016 #define BASE_ADDR_OFF_A_1 014 #define CUR_ADDR_OFF_A_0 012 #define CUR_ADDR_OFF_A_1 010 #define BASE_ADDR_OFF_B_0 006 #define BASE_ADDR_OFF_B_1 004 #define CUR_ADDR_OFF_B_0 002 #define CUR_ADDR_OFF_B_1 000 #define INT_VEC_0 0132 #define INT_VEC_1 0130 /* these two are NOT in manual but are in vms driver */ # define ALLONES 0xffffffff # define BIT0 01 # define BIT1 02 # define BIT2 04 # define BIT3 010 # define BIT4 020 # define BIT5 040 # define BIT6 0100 # define BIT7 0200 # define BIT8 0400 # define BIT9 01000 # define BIT10 02000 # define BIT11 04000 # define BIT12 010000 # define BIT13 020000 # define BIT14 040000 # define BIT15 0100000 /* port_config BITs , abbreviated pc */ #define pc_DMA_BLOCK BIT0 #define pc_DMA_0_EN BIT1 #define pc_DMA_1_EN BIT2 #define pc_TRANS_0_EN BIT3 #define pc_TRANS_1_EN BIT4 #define pc_RESET_0 BIT5 #define pc_RESET_1 BIT6 #define pc_TRANSCOUNT_RESET BIT7 #define pc_FUNBITS_EN BIT8 #define pc_0_FULL_INT BIT9 #define pc_0_OFLO_INT BIT10 #define pc_0_NOTEMPTY_INT BIT11 #define pc_1_EMPTY_INT BIT12 #define pc_1_UFLO_INT BIT13 #define pc_EXT_INT BIT14 #define pc_MASTER_INT BIT15 /* status register BITs, abbreviated st */ #define st_0_NOTEMPTY BIT0 #define st_0_NOTFULL BIT1 #define st_0_FULL_INT BIT2 #define st_0_OFLO_INT BIT3 #define st_0_NOTEMPTY_INT BIT4 #define st_1_NOTEMPTY BIT5 #define st_1_NOTFULL BIT6 #define st_1_EMPTY_INT BIT7 #define st_1_UFLO_INT BIT8 #define st_EXT_INT BIT9 #define st_EXT_BLOCK_MD BIT12 /* BITs 13-14 are interrupt priority BR4 has 0 in both BITs */ #define st_BR5 BIT13 #define st_BR6 BIT14 #define st_BR7 (BIT13 | BIT14) #define st_NONEX_MEM BIT15 /* interrupt clear commands */ #define st_CLR_NONEX_MEM 000 #define st_CLR_0_FULL_INT 001 #define st_CLR_0_OFLO_INT 002 #define st_CLR_0_NOTEMPTY_INT 003 #define st_CLR_1_EMPTY_INT 004 #define st_CLR_1_UFLO_INT 005 #define st_CLR_EXT_INT 006 #define st_CLR_DMA_PEND 007 /* input function register, abbreviated ifn */ #define ifn_FN0 BIT0 #define ifn_FN1 BIT1 #define ifn_FN2 BIT2 #define ifn_FN3 BIT3 #define ifn_FN4 BIT4 #define ifn_FN5 BIT5 /* output function register, abbreviated ofn */ #define ofn_FN0 BIT0 #define ofn_FN1 BIT1 #define ofn_FN2 BIT2 #define ofn_FN3 BIT3 #define ofn_FN4 BIT4 #define ofn_FN5 BIT5 /* mastermode register, abbreviated mm [hi George!] */ #define mm_DMA_ENABLE BIT0 #define mm_SINGLE_CYCLE BIT1 /* the rest of the BITs in mastermode must be set to 0 */ /* channelmode high register, abbreviated cmhi */ #define cmhi_NOMATCH_STOP 01 #define cmhi_MATCH_STOP 02 #define cmhi_HARD_MASK BIT3 #define cmhi_SOFT_START BIT4 /* channelmode low register, abbreviated cmlo */ #define cmlo_FIFO_BIT BIT1 #define cmlo_COMPARE BIT2 #define cmlo_FLIP_BIT BIT4 #define cmlo_INTERLEAVE BIT5 #define cmlo_EOP_INT_ENABLE BIT7 #define cmlo_MATCH_INT_ENABLE BIT8 #define cmlo_TRANS_INT_ENABLE BIT9 #define cmlo_BTOC_EOP_REL BIT10 #define cmlo_BTOC_MATCH_REL BIT11 #define cmlo_BTOC_TRANS_REL BIT12 #define cmlo_CHAIN_EOP BIT13 #define cmlo_CHAIN_MATCH_EN BIT14 #define cmlo_CHAIN_TRANS_EN BIT15 /* command register, abbreviated com note that the command register is write only, it is read as the DMA status register */ #define com_CH_1 BIT0 #define com_CH_0 0 #define com_CLEAR 0 #define com_SET BIT1 #define com_INT_PEND_BIT BIT2 #define com_INT_EN_BIT BIT4 #define com_DMA_RESET 0 #define com_INT_CNTL BIT5 #define com_SOFT_REQ BIT6 #define com_FLIP_BIT BIT5 | BIT6 #define com_HARD_MASK BIT7 #define com_START_CHAIN BIT5 | BIT7 /* chain control word */ #define chain_CHAIN_ADDRESS BIT0 #define chain_CHANNEL_MODE BIT1 #define chain_PTRN-MSK BIT3 #define chain_BASEOPCNT BIT4 #define chain_BASE_ADDR_B BIT5 #define chain_BASE_ADDR_A BIT6 #define chain_CURROPCNT BIT7 #define chain_CURR_ADDR_B BIT8 #define chain_CURR_ADDR_A BIT9