Index of /atarilibrary/atari_cd04/ELEKTRO2/CLA

      Name                    Last modified       Size  Description

[DIR] Parent Directory 11-May-2007 21:03 - [TXT] CLA.PRG 05-Dec-1993 14:48 215k [DIR] CONF_CLA/ 11-May-2007 21:03 - [DIR] DOC/ 11-May-2007 21:03 - [DIR] EXAMPLES/ 11-May-2007 21:03 - [DIR] FSM_DES/ 11-May-2007 21:03 - [TXT] INVENTOR.Y 05-Dec-1993 11:27 3k [DIR] LIBRARY/ 11-May-2007 21:03 - [TXT] LIBV1.PRG 03-Nov-1993 07:05 43k [DIR] RES_CLA/ 11-May-2007 21:03 - [TXT] VECED2.PRG 02-Nov-1993 03:10 54k [DIR] VHDL/ 11-May-2007 21:03 -

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                        CLA Version 2 Release 1 (Beta4)

                       DIGITAL LOGIC DESIGN & SIMULATION
                          For the Atari ST/TT/Falcon.

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Copyright 1993, By Data Uncertain Software.

Written By Craig Graham.

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A short note for the world.

HI...

Here is general release 1 of CLA2 (6/12/93).

(For those of you who had the beta releases, this would be v2r1 beta 4).

If you don't know what CLA is, then read the file DOC\MANUAL.TXT.

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Ta da - here are the fixes to the last set of bug reports I got back. Window
redraw is now greatly improved, and the whole she-bang now feels comfy with
WINX2.1 (if you've not got it - get it - it's really good).

IMPORTANT:

You may distribute this release generally. Please do.

The program still has some uncharacterised bugs, but as far as I'm aware,
nothing which will eat your hard disc :) - see DOC\BUGLIST for details.

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You will require:

BASIC SYSTEM:
	Platform : ST
	Memory   : 2 Meg
	Storage  : DS Drive.
	Display  : SM124 (High Res) or any Min. 400 vertical res. display.
               (Works with MONSTER and other Virtual Screens).
	OS       : Any TOS

I am currently targetting a slightly better machine than this base,
especially display-wise, as 640*400 gets very cramped and, to compete with
IBM applications, there is a large use of TOS4 3D buttons & dialogs for visual
impact.

STANDARD TARGET (Recomended System):
	Platform : MegaSTE / TT / Falcon
	Memory   : 4Meg - required for running CLA at higher res.
	Storage  : Hard drive, requires 1 Meg for basic installation - this
				WILL increase as the synthesis tool & FSM designer are added.
    Display  : Crazy Dots / TT / Falcon extended (FalconScreen/Blowup030)
				@ 800*600 (no problem for a falcon, PD stuff gives this even on
				the very cheapest SVGA NI monitor you can buy).
				+ 16 Colours.
				+ a gfx accellerator (Warp9 / NVDI) 
	OS       : TOS 4.02+, multiTOS 1.04+.

Disclaimers
------------
The development machine is a 4/65 Falcon030 with MultiTOS, NVDI & FalconScreen
so any smaller systems may have problems with memory (2Meg is probably enough
if you don't use MultiTOS) - running in higher resolutions will use more 
memory - so beware. Let me know as soon as possible if there is a problem.

There is currently NO PROPER DOCUMENTATION for CLAv2. This will be rectified
as time goes on & should be supplied to Beta testers as a postscript
file (please request it in a different format if this is a problem -
even ASCII, although you'll lose all the illustrations). This will probably be
accompanied by an upgrade to the VHDL compiler. 
If you don't return my survey (below), then you will not get the manual.
If you're not a beta tester, then you'll have to register to get the proper
manual (but hey - return the survey anyway).

 The v1 documentation is as good a staring point as any - so I have updated it
and modified it to apply to v2, and included it as the file DOC\MANUAL.TXT.
BUT it is still mostly out of date, and doesn't give a full guide.

I very much hope that you will be able to try some of the new features
(which 'should' now work on most systems).

The file 'CHANGES.TXT' contains a list of new features from v1r1.

The file 'BUGLIST.TXT' contains (surprise!) a list of bugs that I know
about. I would hope that you will read this & report any new ones (that
is the main condition of being a Tester :) )

Please feel free to complain bitterly at my lateness in producing this,
but please take into account the fact that I have a job & a Master's Degree
to take up my time as well as working on this monster......

Enjoy my baby - I'm quite proud of it.

CRAIG GRAHAM.
email:craig.graham@newcastle.ac.uk
smail:Craig Graham
		46 School Rd
		Langold
		Worksop
		Notts
		S81 9PY
		ENGLAND.
TEL:(UK) (0909)732788 - This is NOT my number, it's my parent's. But if
                        you ask, they'll tell you my current number (it
                        changes often).

PS All Beta Testers (and anyone else for that matter) are requested to return 
     the survey below in order to provide me with some feedback.

PPS For those of you without multiTOS or TOS4, there are three screenshots
     included to show you what you're missing.
     DOC\TOS4SCR1.GIF,  DOC\TOS4SCR2.GIF & DOC\FSM_EDIT.GIF
     - 16 colour GIF's, use GEMVIEW to view them. Snapshots taken with 
     XIMG-Snapshot by S.Becker & D. Sabiwalsky, then converted to GIF.

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CLA : A SURVEY - Please fill in and return via email or smail

There are a few things I'd like to do but haven't as yet, here's
you're chance to influence my direction over the coming monthes.
(Or even get in on the act yourself if you like).

0) What system are you running CLA on ?
   Computer:        ST/MegaST/STE/MegaSTE/TT/Falcon/Emulated Atari (Gemulator)
   Processor:       68000/020/030/040
   Speed:           (in MHz)
   Memory:
   Graphics mode:
   Monitor:         TV(f030 only)/SM124/SVGA/MultiSync
   Hard Drive Size: 


1) VHDL is an up and coming design approach. Should I work towards greater
   support from CLA for VHDL ? 
   (eg. Run CLAVHDL concurrently with CLA with message passing to allow
   interaction between the two, and a more complete implementation of the
   language)



2) State diagrams can also be useful to represent certain aspects of hardware
   or systems design. Do I integrate them into CLA ?



3) GalaxyCAD can synthesis EPLD's. and will shortly have FPGA support.
   Comercial packages can synthesis everything
   (PLD, FPGA, ASIC). This seems to be the way to go. How should CLA support
   this route ?

      i) Export of netlists in sythesisable VHDL to allow a comercial
         package to do the synthesis.

      ii) Integral sythesis of PLD's.
          (Note: If there is a need for this, myself & Peter will
           require help 'coz we don't know how to approach this)

      iii) Export Galaxy compatible files to allow synthesis into EPLDs
		   using Galaxy's Intel EPLD synth. facility.

      iv) Synthesise & then export PALASM files as FSM-EDIT does now.

      v) Forget it & stick to simulation.


4) What simple tools are missing from CLA (from a schematic capture viewpoint)?



5) What simple tools are missing from CLA (from a simulation viewpoint)?



6) Advanced wishlist:- what features of advanced comercial electronic design
     and simulation packages would be most lusted after?


7) What is your job description?


8) Company name ?


If you in the electronics industry then please answer the section below:


9) What Schematic capture tool(s) do you use?
    Mentor Graphics                 [ ]
    Altera                          [ ]
    Dazix/Intergraph Ace/AcePlus    [ ]
    Galaxy CAD                      [ ]
    Other .....:

10) What State Machine design tool do you use?
    SPeeDCHART                      [ ]
    Translogic                      [ ]
    Dazix/Intergraph
       Design Expresions V12        [ ]
    ABEL                            [ ]
    Other.....:

11) Which VHDL/HDL modelling system do you use ?
    Mentor Graphics                 [ ]
    Dazix/Intergraph Advamsim       [ ]
    Alliance                        [ ]
    ModelTech                       [ ]
    Verilog HDL                     [ ]
    Other.....:

12) What Synthesis Tools do you use ?
    Exemplar                        [ ]
    TransGATE                       [ ]
    Alliance                        [ ]
    Cadence                         [ ]
    Dazix/Intergraph Synovation     [ ]
    Asyl                            [ ]
    Minc                            [ ]
    Synopsis                        [ ]
    Cadence                         [ ]
    NeoCAD (also routing)           [ ]
    Other.....:

13) Which simulator do you use?
    Mentor Graphics                 [ ]
    Dazix/Intergraph Advamsim       [ ]
    Galaxy                          [ ]
    Alliance                        [ ]
    Other.....:

14) What technologies do you work in ?
    PAL/PLD/EPLD
    (Small scale - eg 22V10)        [ ]
    PLD/EPLD 
    (Large scale - eg Altera Max)   [ ]
    FPGA (eg Xilinx 3000)           [ ]
    ASIC (semi-custom)              [ ]
    ASIC (full-custom)              [ ]
    Other.....:
    

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Thankyou for taking the time to answer this - it'll be a big help in knowing
what to do next.

I'll mail the survey results to all Beta Testers and interested parties, those
in the industry may find the results of the final section interesting - I'm
really just being nosey as well in that section :).

(We use the Integraph & ModelTech stuff here at BAe Space Systems, so there!).

Craig Graham

Microelectronics & Software Engineer, 
 BAe Space Systems (CommSats Division),
 Stevenage,
 England.

Student (MEng Microelectronics)
 Newcastle University, 
 Newcastle Upon Tyne,
 England.