Changes In Verilint
===================

4.20 (4/5/1998)
----

1. Now Verilint has a better return code as follows:

  The 8 LSB's of which are an integer as follows:

  0: No errors or warnings
  1: No license available
  2: No valid license
  3: No license server found
  4: Unable to run
  5: Abnormal termination (core dump)
  6: Fatal error
  7: Syntax error(s)
  8: Semantics error(s)
  9: Runtime error(s) (for simulation, etc)
 10: Error in a subprocess. 
 11: Out of memory
 12: Veribase error
 16: Warning(s)

 The MSB's value depend on the LSB's error code.

2. Now Verilint supports user defined warning sets. A warning set is a
   named set of warning numbers. Such a set can be defined by the user
   using command-line options. A warning set can be disabled or enabled
   using command-line option. The following command-line options have been
   added or changed:

   +wgroup+set1+myset+yourset  -- Declare (new) warning sets set1, myset, yourset
   +set1+23+56+274             -- Add warnings 23, 56 and 274 to set1
   +show_groups                -- Show all the declared warning sets
   -wset1                      -- Disable the warnings in set1

3. Now Verilint supports the `file directive. The format is

   `file <filename> <linenumber>

  e.g.

   `file newfile 56

  This resets the file name and line number in the parser. It can be used
  if Verilint runs on pre-processed Verilog files.

4. Now Verilint does not issue an erroneous warning 496 when a case item
  expression has x's and z's.

5. Now Verilint issues a warning 496 if x's or z's are used in comparison
  expressions. E.g. the following if condition will always be false:

   if (a == 2'bxx)

6. Now Verilint can generate files that represent the hierarch of the design.
  Such files can be used by other tools such as GUI browsers. The two
  command-line options for generating the hierarchy files are
  +module_hierarchy_file and +instance_hierarchy_file. For example

     > verilint +instance_hierarchy_file+ifile +module_hierarchy_file+mfile

  will create two files: mfile is a text file containing the names of all
  the modules and their locations (file and line number), and ifile is a
  text file containing all the instances and their locations.

7. Now Verilint can show all the disabled warnings using the command-line
  option +verilint+show_disabled.

8. Now Verilint handles correctly tasks with real inputs. It used to issue
  errors of "Symbol already defined".


4.10
----

1. Now verilint_n does not crash when a function calls another
   function that is declared later in the code.

2. Now warning 599 is masked when the -ls option is used.

3. Now verilint handles correctly library files and does not print
   dummy or null file names in the warning/error messages.

4. Now Verilint does not print (bogus) messages regarding inferred
   flipflops if the always block does not have any assignment
   statements in it.

5. Now Verilint can handle constants with embedded macros as follows:
     `define abc 1100
      ... 4'b`abc
   Previously Verilint flagged it as a syntax error.

6. Now Verilint hadles correctly multiple -y options on the command
   line. Previously Verilint sometimes could not find some of the library
   files.

4.09
----

1. Now Verilint handles missing arguments to the -f, -y and -v command
   line options.

2. Verilint issues a warning if the operands of a divide or modulo
   operation are not constants.

3. Now Verilint handles the -L option. This disappeared in 4.08.

4. Now Verilint handles constants which have NL (\n) between the
   base and the number. E.g.

    4'b
    0110

   Previously, this caused a crash if it happened to be in the case
   expression.

5. Now Verilint handles correctly range or bit-select in a parameter
   that was declared without a range. For example

   parameter p = 4'hD;
   ... p[2] ... p[1:0] ...

6. Now Verilint handles very wide variables in a limited way. A
   declaration of the type "reg [1000000000:0] r;" would cause Verilint
   to "hang" since it needed to initialize a large array which had one
   element per bit (for example to make sure that every bit of the vector
   has been set and used). The new version has a default value for
   maximum width of 10000. It can be increased using the plus
   command-line option max_var_width as follows:

       +max_var_width+1000000000.

7. Verilint_n performance has been optimized

8. Some of the +verilint options have been changed. In particular the
   options:

        +verilint+first_in_module_only+... has been changed to
        +verilint_first_in_module_only+..., the option

        +verilint+all_in_module+... has been changed to
        +verilint_all_in_module+..., the option

        +verilint+first_in_design_only+... has been changed to
        +verilint_first_in_design_only+... and the option

        +verilint+all_in_design+... has been changed to
        +verilint_all_in_design+...

9. All the options are shown when Verilint runs without
   arguments.

10. Delays now produce only warning #257 (Delays ignored by synthesis
   tools) and not #599 (This construct is not supported by Synopsys).
   The two messages were redundant.

11. Now Verilint checks and issues an error for a system function call
   which has no arguments, e.g. $random().

4.08 (12/9/97)
----

1.  VG 1.15  (Verilint Graphical)
    a.  Made all RCS commands user-configurable in ".vg".
    b.  Now correctly displays file after linting with new arguments.
    c.  Now updates file selection button more intelligently after
        linting with new arguments.
    d.  No longer forces users to quit when no warnings are found.
        Instead, the user can edit the sources and re-lint with the 
	same or different arguments.
    e.  Added line wrapping option to Preferences/Lint
    f.  Improved message when "verilint" executable is missing.

2. Detection of latches is more accurate. For example, the sequence
   "if (a) b=1; b=0;" does not report a latch generation.

3. Verilint_n no longer gives a false warning on multiple concatenation
   e.g. "z = {15{y}};"

4. Verilint_n gives better warnings when an expression is truncated but
   no significant bits are lost.

5. Verilint_n gives better warnings when a decimal integer is converted to
   a bit if the integer is 0 or 1.

6. Verilint no longer gives false error messages if the second or third 
   argument is a vector.

7. Verilint_n now correctly handles the -y, +define, +incdir and
   +libext command-line arguments.

8. Verilint now processes macros that have double quotes in them
   even if the macros are defined on the command line:
   +define+abc=\"xyz\"

9. Verilint now handles "sticky_off" comments which refer to illegal
   warning numbers.

10. Both Verilint and Verilint_n now use the new command-line processing
    routines. This ensures better future compatiblity and robustness.

11. Now verilint_n understands the -w and -wnnn (e.g. -w123) command-line
    options. Currently working on a solution to support for //verilint 
    comments.

12. Now verilint issues the right warning when a port in an instantiation
    is connected to a NULL expression. Previously, when reporting the port
    name, Verilint used the position of the port in the instantiation rather
    than the position of the port in the module.


4.07 (10/27/97)
----

1. Now Verilint handles correctly warnings that are disabled by comments.
   Previously, Verilint sometimes kept these warnings disabled even after
   an enabling comment was present. This happened when the warning was
   supposed to have been issued only once, or once per module.

2. Now verilint -L handles correctly integer inputs to tasks. Previously
   they were printed as integers but not as inputs.

3. Now Verilint handles correctly parameters that are more than 32 bit wide.

4. Now Verilint handles correctly events (previously, under some
   circumstances the  program crashed.

5. Now vpp has the command-line option +mangle_names to mangle
   upper-case names so that they are distinguished from equivalent
   lower-case names.

6. Added the command-line option +make_instance_names+ which causes instance
   names to be generated for those instances (of gates and UDPs) which do not
   have names. Using +make_instance_names+ causes the generated names to be
   inst_0, inst_1, etc. Using +make_instance_names+aaa causes the generated
   names to be aaa0, aaa1, etc.

7. Added the plus command line option +no_subtree that in conjunction
   with +top_module+... either processes the whole subtree below the
   top or only the top module itself. For example, using

     > verilint -L file... +top_module+m +no_subtree

   will pretty print only the top module without its submodules.

8. VG 1.14:
   a.  Preferences and Help windows now stay on top when moving
       mouse to main window.
   b.  Fixed problem which caused .vg file to sometimes get truncated.
   c.  Improved file selection box for Disableds/{Load,Save}.

9. Now Verilint issues a different warning when not all the cases are covered
   in a synopsys full_case.

10. Now Verilint handles expressions like $time().

11. Now Verilint_n can check out a turbo license.


4.06 (8/29/97)
----

1. Now Verilint does not issue a syntax error when it encounters a DEL
   (\177) character inside a string.

2. Now Verilint handles correctly library (-y) files.

3. Now Verilint handles correctly integer parameters with ranges:
     parameter [2:0] p = 5;

4. Now Verilint detects correctly tristate buffers if the 'z
   expression is a parameter. E.g:

     parameter p = 8'fzz;
     assign a = ctl ? b : p;


4.05 (8/19/97)
----

1. Verilint can now handle correctly constants which have embedded
   macros. Previously, the construct

     `define a 5
     ...
     `ab'00110

   caused a syntax error. Now it is accepted as legal code.

2. Verilint_n now does more width related checking in parametrized
   instances. Previously some of the checks were disabled.

3. A warning for redundant self assignment of the type "a = a;" has
   been added. This warning (#631) informs of the potential reduction in
   simulation speed due to such assignment, and is issued in sequential
   blocks. In combinationa blocks an older warning (#483) is issued to
   the effect that such a construct may cause latch inference.

4. Now Verilint_n does not issue an extreneous warning when a sized
   decimal constant is assigned to a vector of the same width:

     {a, b} = 2'd0;

5. Verilint now handles correctly tristate bus variables that are
   dotted names.

6. Verilint now handles correctly an integer output. Previously, the
   construct

     output [31:0] a;
     integer a;

   generated an error message for a previously defined variable.

7. The plus command-line option +scan_libraries was added. Normally,
   when any error is encountered, then the libraries are not scanned.
   With this option, the libraries are scanned and linted even if there
   are errors.


4.04 (8/7/97)
----

1. Now Verilint treats multiple plus options as a single plus option with
   multiple arguments. For example, previously the two command-line
   options:

   +pli_task+abc +pli_task+efg

   would have meant that only the first one (+abc) would be used and
   the second one (+efg) would be lost. Now these two options are
   equivalent to the one option:

   +pli_task+abc+efg

   The advantage of the new interpretation is that there is no need
   for long command lines if there are many plus arguments.

2. Now when Verilint cannot resolve a dotted name, it issues a warning
   rather than an error. Verilint does only partial search for dotted
   names. It searches either from the current module down or from the top
   level module. It does not do up search which may be legal Verilog.
   For example, the name a.b.c will be found only if either a is a top-
   level module, or if a is an instance in the current module, but not if
   a is an instance in an upper-level module. In the last casem, a warning
   (W629) would be issued (as opposed to an error in the past).

3. Now the comments "//verilint all off", "//verilint all on" work correctly.
   In addition the following form was added:

   //verilint all sticky_off

   The latter is analogous to //verilint i sticky_off

4. Added a new warning when an instantiation has a NULL connection:
   mm u1 (.a());
   Warning 630 now says "Port connected to a NULL expression".

5. Verilint now can handle backslashes inside strings, e.g. "\a" and
   does not issue a syntax error.

4.03 (7/17/97)
----

1.  The sticky_off comment now works inside `include files.

2.  Warnings 627 and 628 were added to report multiply driven tristate
    nets. These warnings are disabled by default (they can be enabled
    using the +w627 and +w628 command-line options).

3.  Verilint now report syntax errors inside libraries even when the
    -wl command-line option is used. All non-syntax errors are still
    disabled.


4.00 (4/8/97)
----

1.  New command-line option "-wi" disables all information messages.
    For example the message "A flipflop is inferred" is disabled. Note
    that the message "A latch is inferred" is considered a warning and
    is not disabled by -wi.

2.  New command-line plus option specifies non-synthesizable modules.
    The option +non_synthesizable_module+a+b... speicfies that modules
    a, b, ... are non-synthesizable modules. All synthesis related warnings
    are disabled inside these modules.

3.  Eliminated extraneous warnings about "Not all the bits of the
    variable are in the sensitivity list".

4.  Linux Verilint now can use the same version of license keys as other
    Unix versions (slipped into 3.14a release May 30).  Does not interfere
    with installations where older keys have already been successfully 
    installed.

5.  Released VG 1.07:  
    a.  Now creates temporary files in directory mentioned in environment 
        variable instead of the current directory.  VG first checks if
        VERILINT_TMPDIR is set, then checks TMPDIR.  If neither is set,
        VG defaults to /tmp.
    b.  Added "Help/About..." dialog and --version command line argument.
    Released VG 1.08:
    c.  VG no longer continues to display an old file when a new file
        is selected and the old file is read-only.
    d.  Improved speed of "read only/writable" and "checked in/out" 
        transitions when a user displays a new file.
    e.  Removed references to Hierarchy browser from help text.
    f.  Informs user of bad ~/.vg startup file and provides option to 
        either overwrite with a valid file (where the computer does a
        repair) or quit (where the user can do a manual repair).
    g.  Improved file displaying mechanism for cases when a user selects 
        to view a file which has had its Verilint output filtered out.
    Released VG 1.09:
    i.  Improved loading speed.
    j.  Added "Continue" option when "verilint" returns with nonzero exit
        status.  Is useful for cases when shared libraries are not quite 
        up to date.
    k.  Now does not require "vtcl.crpt" file to run.
    l.  Eliminated nearly all screen flickering.
    m.  Added graceful recovery for bad ~/.vg file.
    n.  Added "Linting/xx errors, yy warnings" indicator.
    Released VG 1.10:
    o.  Now sorts multi-line warnings (that use "^---") properly.
    p.  Added support for Info "(Ixxx)" fields, which are displayed
        unmodified and can point to a file/line if desired.
    q.  Fixed run time error in help system introduced in 1.09.
    Released VG 1.11:
    r.  Fixed context sensitive help problem where arrow pointer would
        not return. 
    s.  Fixed Edit/{Cut,Copy,Paste} error message.
    t.  Improved context sensitive help.
    u.  Added support for RCS ,v files in current directory.
        (files in RCS directory take priority over files in current directory)
    v.  Updated to use Elan 4.x libraries.
    Released VG 1.12:
    w.  Added support for files that do not have errors/warnings.
    x.  Improved recovery when Save operation fails.

6.  Verilint no longer flags the `uselib directive as an error. `uselib
    is currently ignored by Verilint.

7.  Verilint can now handle complex expression in tristate controls.
    Control expressions can be "name", "name==const", "name!=const",
    "~name" and "!name"

8.  Verilint no longer issues extraneous warning messages for multiply
    driven nets if the net is a tristate net.

9.  Negative indices are now reported as warnings and not as errors.

10. Verilint now handles correctly the case when the two Synopsys
    directives parallel_case and full_case are given in one comment

11. Verilint now detects tristate buses generated with if statements.
    Previously Verilint detected tristate buses only in continuous
    assignments.

12. Verilint no longer issue warning 498 ("Not all the bits of the
    vector are used") if the vector is an output.

13. Verilint now warns (W575) if an operand to a logical-not operation
    is a vector of more than one bit.

14. Verilint now warns (W576) if an operand to a logical binary
    operation (||, &&) is a vector of more than one bit.

15. Verilint now issues an error when an instance name is in the
    sensitivity list.

16. Verilint now does not give a spurious warning of unused input if
    the input appears in a posedge expression in a timing check item.

17. Verilint now does not give a spurious warning if a variable is in
    the sensitivity list and it is not used in the block, if the variable
    is a notifier (in some timing check item).

18. Verilint now quits gracefully when it encounters unrecoverable
    syntax errors.

19. Verilint now handles files with multiple slashes, e.g. .//abc.v

20. Verilint now issues an error when a -y argument is not a directory

21. Verilint now issues an error when a Verilog file is a directory rather
    than a regular file

22. Verilint now detects redeclaration of range in implicit continuous
    assignment: "output [3:0] a; wire [4:0] a=c;"

23. Verilint now obey sticky_off comments for warnings inside macros. Note
    that you cannot use regular "off" comments since macros are treated as
    small files.

24. Verilint now checks for self assignment (a = a;). This can cause
    the inference of a latch.

25. Verilint now can handle conditional expressions in parameter
    declarations: parameter p1=1, p2=3, p3=(p1>p2)?p1:p2;

26. Verilint now checks for a constant (or parameter) in a sensitivity list.

27. Verilint no longer crashes if an integer array element is present
    in the sensitivity list.

28. Verilint now reports an integer variable missing from the sensitivity
    list.

29. The warnings "Not all cases covered" and "Not all cases covered but
    default exists" ahve been split into two warnings each, one, when
    the case statement is a Synopsys parallel_case and one when it is
    not. If the case is parallel, then the warning is less sever, and
    people may want to disable it.

30. Verilint no longer gives an erroneous message: "UDP initialization
    of a non-output variable".

31. The -u now operates correctly. All names are changed to lower case.

32. Case expressions are limited to 31 bits.

33. Verilint now detects when a loop variable is modified inside the
    loop (warning 601).

34. Now the -L option works in conjunction wit +top_module. For example,
    saying -L +top_module+mm will print the whold subtree underneath mm
    including mm itself.

35. Verilint now prints the "Usage" message if a -help command-line
    argument is used.

36. Verilint now issues a warning if the timescale unit is smaller
    than the precision.

37. Now built with Elan 4.1.3 license libraries.  This fixes many problems
    with redundant-servers licenses.  However, this requires Verilint
    to check out licenses from an "ilmd" license server that is at
    version 4.1.3 or newer (to check, run "ilmd -i").  Older versions of 
    Verilint can check out licenses from the newer license server, but 
    not vice versa.

38. Verilint now has a new command-line option +verilint+report which
    generates a report for all the processed modules.


3.14  (5/6/96)
----

1.  Verilint now issues a warning when a zero width based number  
    (e.g. 0'b1) is extended to a width of 1.  Previously Verilint 
    extended the number to a width of 32 without giving a warning.

2.  Verilint now correctly handles an instantiation in which the 
    name of an instance port is not a legal module port name.  E.g:

    module m;
    mm u1(.x(x));   // x is not a port name for module mm
    endmodule

    module mm(y);
    input y;
    endmodule

3.  Verilint now correctly handles the case of case (abc.dd) when 
    abc is an undeclared module.

4.  Verilint -L and -Ls now correctly generate output for nested  
    named blocks.  Also with -Ls, "verilint -Ls" prints a named 
    block comment giving the  encrypted name of the block and not
    the original name.

5.  Verilint now issues a warning when a variable is referenced in
    a nonblocking assignment, and was previously assigned, but is 
    not in the sensitivity list.  If the variable is referenced in 
    a blocking assignment no warning is issued (this is consistent
    with Synopsys).  For example:

    always @(a) begin
      b <= a;
      c <= b;
    end

    will cause a warning because b is not in the sensitivity list, 
    but the following will not:

    always @(a) begin
      b = a;
      c = b;
    end

    In the second case, b is set before it is being used and is 
    therefore assumed to be a temporary variable, internal to the 
    block.

6.  Verilint now reports if a variable is assigned both in blocking 
    and nonblocking assignments.

7.  Verilint now correctly handles the case of one bit parameters:

    parameter [0:0] p=1'b0;

8.  Verilint now correctly handles the various comments for disabling
    and enabling Verilint reports.  In particular, any combination of
    "//verilint <warning#> off",  "//verilint <warning#> sticky_off" 
    and "//verilint <warning#> on" is handled correctly.

9.  Verilint no longer issues a warning of a potential loss of 
    carry/borrow for add/subtract operator if either the source or 
    the destination is an integer.

10. Verilint no longer issues a warning if a shift operator is 
    guaranteed not to cause loss of bits.  This happens when both of
    the operands of the source are constants and the result can be 
    calculated at compile time.  For example, the following will not 
    generate a warning:

    reg [4:0] r;
    ...
    r = 5'b00010 << 3;

    but the following will generate a warning:

    reg [4:0] r;
    ...
    r = 5'b00100 << 3;

11. Verilint no longer issues extraneous warnings about tristate 
    constructs.

12. Verilint no longer issues warning 552 when the driving block 
    is an instance or a gate instance.

13. VG: Changed text in Preferences/Lint Mappings button to a 
    more descriptive "Err/Warn#" and "Line#" from "Code" and "Line".

14. Verilint now issues a warning when some but not all of the bits 
    of a variable are being used.


3.13  (4/1/96)
----

1.  Verilint Graphical no longer requires two licenses.  This was the
    case in 3.11 and 3.12.

2.  Verilint no longer prints the messages:

    Processing source file p.v
    Processing source file gcps.v
    ...

    if the -q (quiet) command-line option argument is present.

3.  Diagnostic messages improved.

4.  Verilint no longer issues a warning when a single bit vector is 
    assigned to a single bit variable.

5.  -f option now functions properly on Verilint PC.

6.  Added filename wildcard expansion to Verilint PC.

7.  Eliminated the bogus "Strange Error" message in Verilint PC that
    occurred when a hardware key was not plugged in.

8.  Verilint PC now responds to ctrl-break much more quickly.

9.  Verilint no longer warns if bits of signals are assigned in different 
    continuous assignments (warnings 552 and 553).  Such warnings are now 
    given only if the assignments are done inside "always" blocks.

10. Verilint has new warnings (554 and 555) which are issued when a
    function is being assigned (using "assign" statement rather than using 
    the "=" sign).  Such an assignment is unconventional and its semantics
    are not clearly defined in the language.

11. Verilint now has a new warning (556) for a complex condition expression.
    This can happen inadvertantly when the user misinterprets the operator 
    precedence.  For example, the expression "a + b?c:d" may be intended to
    be "a + (b?c:d)" but is actually interpreted as "(a + b)?c:d".

12. Verilint -L now handles the license acquisition correctly for all 
    license features.

13. Verilint now correctly handles a -f file that contains "*.v" in it.

14. Verilint now correctly handles error messages when declarations are 
    outside module declarations.

15. The license manager now flushes "Checking out license" and "Done" 
    messages right away.

16. Verilint now detects an error when an array name is used illegally:

    reg [7:0] r [0:25];
    ... $display(r);... r = ...;... a = r;

17. Verilint no longer gives spurious warnings of "Destination variable 
    is input" if the variable is an argument to a PLI task.

18. Verilint now gives a warning when a bit-select or range-select is
    applied to a scalar parameter.

19. Verilint no longer issues a warning if a macro is defined multiple 
    times and all the definitions are identical.

20. Verilint now issues the correct warning when an integer case 
    expression is out of range by 1:

    reg [3:0] state;
    ...
    case (state)
    16: ...  // The largest value for state is 15
    ...


3.12 (2/1/96)
----

1.  Added the warnings:

    "Different bits of a net are driven in different blocks (harmless,
    but some synthesis tools generate a warning for this)"

    and

    "Different bits of a flipflop are driven in different blocks
    (harmless, but some synthesis tools generate a warning for this)"

    Previously Verilint only warned when THE SAME bit of a vector was
    driven by two blocks.  It turns out that Synopsys generates a
    (erroneous) message even when two DIFFERENT bits of a vector are
    driven by two different blocks.  These new warnings reflect the
    Synopsys warnings.

2.  Verilint now correctly handles the case when a -f file does not
    exist.

3.  Verilint now displays only one error message when an undefined task
    is enabled.

4.  Verilint now correctly handles a bit-select expression containing
    function calls: a[f(3)].

5.  Verilint now correctly handles a +define command-line argument that
    contains spaces: +define+a="b c"

6.  Verilint now correctly handles a +define command-line ar- gument
    that contains a directive: +define+a='`timescale 1ns/1ns'

7.  Added warning W280: "Delay in non-blocking assignment".  This
    happens when a non-blocking assignment has a delay in it.  The delay
    is not usually needed in synthesizable code.  Example:

    a <= #1 b;

8.  Verilint now correctly handles the comments "//verilint all off"
    and "//verilint all on".

9.  Verilint output has been reformatted slightly (", line" added
    before the line number) to allow the use of emacs "compile" and "C-x '"
    commands to navigate to the source code error and warnings lines.

10. Released VG 1.05:

    (a) VG changed to work with new (and old) verilint output formats.

    (b) VG No longer prints "can't read vfx(rcsfile): no such element in
        array" under certain conditions.

11. Verilint now correctly handles dotted names in tasks and
    functions.

12. Verilint now prints a nicer error message if the error is inside a
    macro.  The new error message is also emacs friendly.

13. Verilint now issues an error when a module instance name is
    missing.

14. Improved the checking of width of variables in assignments.

15. Verilint now handles Synopsys directives more accurately.


3.11  (1/1/96)
----

1.  Upon exit, Verilint now returns the sum of errors and the number of
    warnings as the exit status. Previously Verilint returned 1 if there
    were any errors and 0 otherwise, regardless of the number of warnings.

2.  Verilint now processes libraries in the same order that they appear
    on the command-line.   Previously it processed them in reverse order.

3.  Added the warning "Redundant case expression" for instances when
    two expressions in a single case item are the same:

    case (i)
    1'b1, 1'b1: ...
    ...
    endcase

4.  Added a warning when a variable in a case item expression is not 
    declared in the sensitivity list.

5.  Released Verilint Graphical 1.04b with Verilint 3.11.  Changes:

    1.  Now defaults to emacs keybindings when the editor specified in
        the .vg file does not exist.
    2.  An error message no longer appears when bringing up a file 
        dialog box.
    3.  The X11 library is now linked statically on the HP platform.

6.  Enhanced error handling for undeclared ports, and eliminated
    extraneous warnings after an undeclared port error was issued.

7.  Warning 521 ("Not all the bits of the variable are in the sensitivity
    list") no longer gives extraneous warnings.

8.  Verilint now correctly reports the line number when issuing parsing
    related warnings such as "Unrecognized Synopsys directive".


3.10  (11/29/95)
----

1.  Added a new plus command-line option "+missing_file_ok", which causes 
    Verilint to continue processing even when it cannot open one of the 
    input files.  By default a missing file is a fatal error that causes 
    Verilint to stop processing and quit.

2.  Added a new plus command-line option "+generate_file_list", which
    causes Verilint to generate a list of the files that were used in
    the processing.  The output can be used to collect all the files 
    used in a simulation into a single directory.  For example, a 
    customer can use it to send interHDL a test case.  Typically, it
    will be used in conjunction with the -q option.

3.  Added a warning for dangling else statements:

    if (a)
      if (b)
        ...
    else  // The indentation is wrong. This else belongs to the second if
        ...

4.  Added a warning for RTL constructs inside gate-level designs.

5.  Added a warning for truncated leading zeros in a constant.  For example, 
    3'h0 will cause this warning.  Note that Verilint has always warned 
    about truncated leading ones (e.g. 3'hf).

6.  Added a warning when a "|" or "||" is used in an event expression. 
    The warning says "Probably intended 'or'...".

7.  Added the warning "Not all the bits of the variable are in the
    sensitivity list".

8.  Added the warning "Variable set but not used".  In previous versions, 
    this case was lumped together with "Unused variable", namely variables 
    that were neither set nor used.  Now Verilint has more granularity.

9.  Added the warning "`ifdef may not be supported by some synthesis
    tools", to reflect the fact that Synopsys does not support `ifdef.

10. Added an error message for a missing `timescale directive after a 
    `resetall directive.  Previously, `resetall was treated as an
    unsupported directive.

11. Added an error message for cases when an input or inout is declared
    as a reg.

12. Added error messages for illegal statements inside a function 
    (delay, event, task call and wait statements).

13. Updated the printing of event-control statements when using the -L
    option (the '@' was missing).

14. Released Verilint Graphical 1.02 with Verilint 3.09a.  Changes:

    1.  Added and improved Emacs and Windows keybindings.
    2.  Added horizontal scrollbar for text editing window.
    3.  Verilint Graphical now runs faster.
    4.  Will select "closest match" colors when colormap is taken by another
        application (Netscape and Framemaker tend to grab the entire colormap
        for themselves).
    5.  Now lints files beginning with the letter "t".
    6.  No longer has "vi" mode in Preferences.

15. Released Verilint Graphical 1.04 with Verilint 3.10.  Changes:

    1.  Added support for the GNU Revision Control System (RCS).
    2.  Added new menu item "New verilint arguments" that lets users
        rerun Verilint with different arguments without exiting VG.
    3.  Added real time monitoring of permission changes for files
        being edited -- provides visual indication of read-only and
        checked-out files.
    4.  Color support is now independent of X server color database, 
        and can be user-extended in the preferences file "~/.vg".
    5.  Nondestructive keystrokes no longer turn on "Save needed" flag.

16. "verilint" and "vg" are now linked statically to avoid warnings 
    about old libc.so shared libraries.

17. Verilint now does not treat "pullup" and "pulldown" as drivers. 
    This eliminates extraneous "Multiply driven nets" warnings.

18. Verilint now flags a notifier in a timing check as being set. 
    This eliminates extraneous warning messages about unset variables.

19. Verilint now correctly handles array elements in the sensitivity list.
    It used to treat them as bit-select expressions and issued warnings 
    about "bit-select in the sensitivity list".

20. Verilint no longer issues a Signal 11 when a shift operation with
    a constant argument is performed.


3.09  (10/27/95)
----

1.  Added a warning when a decimal number is truncated, e.g. 2'd4.

2.  Added the following to the list of recognized Synopsys comments:

    // synopsys async_set_reset
    // synopsys sync_set_reset
    // synopsys async_set_reset_local
    // synopsys sync_set_reset_local
    // synopsys async_set_reset_local_all
    // synopsys sync_set_reset_local_all
    // synopsys one_hot
    // synopsys one_cold

3.  Added a check for illegal usage of the "or" operator.  When an 
    expression like "a & b or c" is encountered, Verilint issues an error
    and suggests the use of "|" or "||".

4.  Added a check that issues a warning when the sensitivity list has a 
    bit-select (a[2]) or a range-select (a[2:4]).  Although this is legal
    Verilog, Synopsys requires the full vector.

5.  Added a check for the following syntax error:

    module TriBus ( clk, reset, .OutEnable, TriBus, InData );
    input clk, reset, OutEnable, TriBus, InData;
    endmodule

6.  Released Verilint Graphical 1.01.  Changes:

    a. Tries a default X display if DISPLAY environment variable not set.
    b. "vg" error messages are more detailed.
    c. Runs Verilint with +verilint+all_in_module to show all cases of
       repeated warnings.
    d. Displays several warnings with improved clarity (special cases 
       such as warnings in macros).
    e. Searches for "verilint" in the same directory where "vg" was run --
       then tries searching the PATH.
    f. Handles PATH environment variable of any length.

7.  Improved readability of Verilint output by no longer processing 
    libraries when syntax errors are encountered.

8.  Improved linting of expressions with parameters.

9.  Changed the warning "latch detected" in functions to a more accurate
    "A variable has not been assigned in all the paths in the block".

10. Changed the return value type of $test$plusargs to VID_REG and the
    width of the return value to 1.  Previously, the construct
    "if ($test$plusargs(...))" reported "Non one bit expression...".

11. Verilint no longer reports "High Z in constant" when a tristate is
    declared with concatenation or multiple-concatenation.

12. Verilint now lints the parameters in instantiations of modules and
    gates.  This eliminates extraneous warnings of unused parameters.

13. Primitive instantiations with unconnected ports are now processed 
    by Verilint.

14. Verilint now accepts a dotted name when resolved into an instance 
    name (rather than the usual variable name).

15. The -Ls command-line option now accepts designs with an unlimited 
    number of variables.


3.08  (10/9/95)
----

1.  Added the Synopsys comments:

    //synopsys map_to_module BLAH_MODULE
    //synopsys return_port_name BLAH_PORT_OUT

    These comments are now recognized and ignored.  Previously they 
    issued an "Unrecognized Synopsys comment" warning.

2.  Added the Synopsys comments label and resource.

3.  Added the option "--version", which only prints the product name and
    version.  This is used by Verilint Graphical to ascertain that the 
    right Verilint exists and is on the path.

4.  Added more detailed information when encountering a PLI error.

5.  Enabled the printing of multiple warnings for the same type/width
    mismatch.  For example if r is 4 bit variable, then r=1011 will 
    give two warnings: one for the type conversion of the integer 1011 
    to a vector and the second for truncating the resulting 32 bit 
    vector to 4 bit vector.

6.  Enabled the detection of unused macros.

7.  Made all references to Synopsys directives and keywords 
    case-insensitive.

8.  PC version recognizes the new license keys.

9.  The message indicating the number of syntax errors is now sent to 
    stdout and instead of stderr.  Also the number of errors now includes 
    both syntax and semantics errors.

10. Verilint no longer prints the warning message "multibit expression 
    when one bit expected" for data event expressions in timing check 
    tasks ($nochange, etc.).

11. Removed extraneous characters that were printed at the end of the 
    "Unrecognized Synopsys directive" warning (#464).

12. Fixed erroneous warning message regarding "bus variable in the 
    sensitivity list but not all its bits are used in the block" (#488)
    that occurred under some circumstances.

13. Fixed erroneous error message regarding "Not constant expression".  
    This was given for multiple concatenation and some other expressions.

14. Fixed an internal error that occurred when one of the expressions in 
    a timing check construct ($setup, $hold, ...) was a bit-select (a[0]).

15. Fixed an internal error that occurred under some circumstances when a
    a reference was made to an array element.

16. Fixed an assertion error that occurred sometimes when handling 
    parameters that were declared local to a function or task.


3.07  (8/22/95)
----

1.  Added check for ports that are unnamed and unconnected.  E.g:

    module m(a, , b,);
    ...

2.  Added check for a destination bit that is an input.

3.  Added check for multiple drivers to a flipflop.

4.  Added check for an array element used in an always block but
    not in the sensitivity list.

5.  Added better error messages for UDPs indicating if the table entry
    (sequential or combinational) does not match the output (which
    should be reg or wire, respectively).

6.  Enabled processing of multiple Synopsys comments on a line.
    Example: //synopsys parallel_case full_case. 
    Previously only the first one was processed and the second one 
    was ignored.

7.  Removed limitation on macro size. It used to be 1000 characters.

8.  The -L (pretty print) option no longer displays the message 
    "Checking out license...Done", similar to the -q (quiet) option.

9.  If an instance port is unconnected, Verilint now prints the
    port name in addition to the port number.

10. If an error occurs inside a macro, Verilint now prints the 
    location of the macro in the file.

11. Verilint now properly handles quote marks in command line macro 
    definitions such as +define+a="b".

12. Eliminated erroneous error message when the first argument to a
    $readmemb or $readmemh is not a string.  Verilog permits any variable
    or an expression (such as a concatenation).

13. Verilint no longer checks a variable twice if it is a member of a
    reference.  Usage of global variables in a function or task are now 
    detected in all cases.

14. The Windows NT version now recognizes the new license keys.

15. The Windows NT version now provides UNIX-style filename pattern 
    matching on the command line, such as "verilint *.v".

16. The Windows NT version no longer creates an empty file when attempting
    to open a non-existing file.  The result is that +incdir now works.

17. Fixed an internal error caused by a missing instance name following 
    a syntax error:

    module m;
    module c(a);
    endmodule

18. Fixed an assertion error that occurred when a vector index was out 
    of range.

19. Fixed an internal error that occurred under some conditions when an
    array element was used in the sensitivity list.


3.06  (7/10/95)
----
1.  Added command-line option "+top_module+<modulename>".  Using this 
    option, Verilint will lint only the named module and the subtree 
    below it.

2.  Added two command-line plus options, "+verilint+max_case" and
    "+verilint+max_casexz", to control the maximum width of case statement
    expressions to be checked.

    If the width of a case expression is greater than the maximum width,
    the statement will not be checked for uncovered or multiply covered 
    cases, and the warning "case too wide" will appear.

    The default maximum widths are 10 bits for regular case statements
    and 7 bits for casex or casez.  "+verilint+max_case+15" will set
    the maximum size of a regular case width to 15 bits, while 
    "+verilint+max_casexz+10" will set the maximum width of casex and 
    casez to 10 bits.  The maximum widths may be set to any nonnegative 
    integer.  Note, however, that checking wide case statements increases 
    memory use and execution time.

3.  Added command-line option "+verilint+synopsys_translate".

    By default Verilint ignores the Synopsys comments 
    "//synopsys translate_off" and "//synopsys translate_on", unless the 
    command-line option "+verilint+synopsys_translate" is used, in which 
    case Verilint disregards the code between these two comments.

    Note:  In Verilint 3.05, Synopsys comments were always obeyed.

4.  Added command-line option "+verilint+comb_loops" to enable detection of 
    combinational loops.  The default is to not detect combinational loops, 
    which speeds up execution.

5.  Added ability to declare pli tasks and functions without the '$':
    verilint ... +pli_task+abc (instead of +pli_task+$abc).

6.  Added processing of comments like // $S for synopsys. Earlier only
    lower-case $s was handled.

7.  Added check for inputs that are declared multiple times:
      input i; input i;

8.  Added check for declaration outside a module:
      ...
      endmodule
      input i;
      module ...
      ...

9.  Added check for negative range indices.

10. Verilint now recognizes a synopsys comment in which there is more than 
    one space between the "synopsys" keyword and "parallel_case"
    // synopsys  parallel_case
    (W464)  Unrecognized Synopsys directive:  parallel_case

11. Fixed extraneous warnings for unused variables/parameters in
    delays in continuous assignments.

12. Fixed problem with named blocks.

13. Fixed problem with pretty-printing strengths of the form (strong0, highz1),
    e.g:
      module mux2;
      bufif1 (strong0, highz1) (a, b, c);
      endmodule

14. Macro names can now start with a back slash (\).  This is compatible with
    Verilog-XL.


3.05  (6/19/95)
----
1.  Fixed a bug relating to $readmemb, $readmemh and $dumpvars arguments.

2.  Fixed a bug relating to //synopsys translate_on_... comments that
    caused a Signal 11 message.

3.  Added "//verilint all off" and "//verilint all on" to disable/enable
    all Verilint warnings in a region.

4.  Added "//verilint translate off" and "//verilint translate on".
    They are analogous to the Synopsys comments "//synopsys translate_off"
    and "//synopsys translate_on", in the sense that any code between
    these two comments is disregarded without processing by Verilint.
    The Synopsys comments and Verilint comments are independent and can
    be used separately or together.

5.  Added file name and line numbers to some errors/warnings which did
    not show them before.

6.  Miscellaneous bugs fixed.


3.04  (5/26/95)
----
1.  "verilint" and "vg" now recognize new license keys:

    01  Verilint Batch and Graphical   (previously Batch only)
    09  Verilint Graphical Only
    10  Verilint Batch Only
    11  Verilint Turbo
