ATA ID Output Descriptions file

Drive #
Indicates the physical disk drive number, either 0 or 1.

Model Number
Indicates the actuall model number of the drive as recored in the drive indentification header

Serial Number
Indicates the actuall serial number of the drive as recored in the drive indentification header

Media type
Indicates whether the drive media is magnetic or non magnetic (eg. optical)

Drive type
Valid values are removalbe and non removable

Sector formatting
Valid values are MFM encoded or not MFM encoded, with soft or hard sectoring

Able to do double Word Transfers


Maximum Data Transfer Rate
rate > 10 Mbs  
rate > 5Mbs but <= 10Mbs 
rate <= 5Mbs   

Controller Buffer Type
0000h	not specified.
0001h	a single ported single sector buffer which is not capable of simultaneous data transfers to or from the host and the disk.
0002h	a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the disk.
0003h	a dual ported multi-sector buffer capable of simultaneous transfers with a read caching capability.

Controller Cache Buffer Size
Actual size of on board Cache to the nearest 512 bytes.

ECC bytes
The number of Error Correction and control bytes available on a long transfer.  If a value
other than 4 is set, it is unable to determine the current number of bytes used.

Maximum Number of Sectors per Interrupt.
The number of sectors currently set to transfer on a READ OR WRITE MULTIPLE command
If value =8, then 8 secotrs worth of data would be transferred at a time.

Default Translation Mode (recommended by manufacturer)
The number of user-addressable cylinders, heads, sectors in the default translation mode.

Current Translation Mode
How the drive is currently set up.

Current BIOS Setup
what the BIOS thinks is going on.  should equal curent translation mode.

DMA (Direct Memory Access) transfers supported
Yes or No.

LBA (Logical Byte Addressing) supported.
Yes or No.

PIO Data Trasnfer Timing Mode
The PIO transfer timing for each ATA device falls into categories which have unique 
parametric timing specifications.  
Valid values are 0, 1, 2 and 3.  See the table below for timing differences.


                              |<------------ t0 ------------------------>| 
                  _____ __________________________________________       |  
 Address Valid *1 _____X                                          \_________
                       |<-t1->|                           ->| t9  |<-      
                       |      |<----------- t2 ------------>|     |<-t8->| 
                       |      |_____________________________|<---t2i---->|__
 DIOR-/DIOW-      ____________/                             \____________/     
                       |      |                             |
                       |      |                    ____________
 Write Data Valid *2------------------------------<____________>------------
                       |      |                    |<--t3-->|  |          
                       |      |                           ->|t4|<-       
                       |      |                     ____________ ____    
 Read Data Valid  *2-------------------------------<____________X____>------
                       |      |                    |<--t5-->|   |    |     
                     ->|t7|<- |                    |      ->|t6 |<-  |     
                       |  | ->| tA |<-             |          ->|t6Z |<-   
                       |  |__________________________________________
 IOCS16-          ________/        |               |                 \______
                                   |             ->|tR|<-
                   ________________|________________________________________
 IORDY            XXXXXXXXXXXXXXXXX___________________/

*1 Drive Address consists of signals CS0-, CS1- and DA2-0          
*2 Data consists of DD0-15 (16-bit) or DD0-7 (8-bit)                   



     +----------------------------------------------------------------------+
     | PIO                                      |Mode 0|Mode 1|Mode 2|Mode 3|
     | timing parameters                        | nsec | nsec | nsec | nsec |
+----+------------------------------------------+------+------+------+------+
| t0 | Cycle time                         (min) | 600  | 383  | 240  | 180  |
| t1 | Address valid to DIOR-/DIOW- setup (min) |  70  |  50  |  30  |  30  |
| t2 | DIOR-/DIOW-      16-bit            (min) | 165  | 125  | 100  |  80  |
|    |   Pulse width     8-bit            (min) | 290  | 290  | 290  |  80  |
| t2i| DIOR-/DIOW- recovery time          (min) |      |      |      |  70  |
| t3 | DIOW- data setup                   (min) |  60  |  45  |  30  |  30  |
| t4 | DIOW- data hold                    (min) |  30  |  20  |  15  |  10  |
| t5 | DIOR- data setup                   (min) |  50  |  35  |  20  |  20  |
| t6 | DIOR- data hold                    (min) |   5  |   5  |   5  |   5  |
| t6Z| DIOR- data tristate (2)            (max) |      |      |      |  30  |
| t7 | Addr valid to IOCS16- assertion    (max) |  90  |  50  |  40  |  30  |
| t8 | Addr valid to IOCS16- negation     (max) |  60  |  45  |  30  |  30  |
| t9 | DIOR-/DIOW- to address valid hold  (min) |  20  |  15  |  10  |  10  |
| tR | Read Data Valid to IORDY active    (min) |      |      |      |   0  |
|    |  (if IORDY initially low after tA)       |      |      |      |      |
+---------------------------------------------------------------------------+

                       PIO Data Transfer to/from Drive 


DMA Data Transfer Timing Mode

                    |<----------------------- t0 ----------------------->|   
                 ____________                                         _______
 DMARQ       ___/            \_______________________________________/   |   
                    |<- tC ->|                                           |   
                    |______________________________________________      |___
 DMACK-      _______/                                              \_____/   
                    |<--- tI --->|_________________|<----- tJ -----|     |   
 DIOR-/DIOW- ____________________/                 \_________________________
                    |            |                 |                     |   
                    |            |<------ tD ----->|                     |   
 Read               |                      _________________             |   
 DD0-15      -----------------------------<_________________>----------------
                    |            |<- tE ->|<- tS ->|<- tF ->|            |   
 Write              |                  __________________________        |   
 DD0-15     --------------------------<__________________________>-----------
                    |                 |            |             |       |   
                    |                 |<--- tG --->|<--  tH   -->|       |   

     +----------------------------------------------------------+
     | Single word DMA                  | Mode 0| Mode 1| Mode 2|
     | timing parameters                |  nsec |  nsec |  nsec |
+----+----------------------------------+-------+-------+-------|
| t0 | Cycle time                 (min) |  960  |  480  |  240  |
| tC | DMACK to DMREQ delay       (max) |  200  |  100  |   80  |
| tD | DIOR-/DIOW-      16-bit    (min) |  480  |  240  |  120  |
| tE | DIOR- data access          (max) |  250  |  150  |   60  |
| tF | DIOR- data hold            (min) |    5  |    5  |    5  |
| tG | DIOW- data setup           (min) |  250  |  100  |   35  |
| tH | DIOW- data hold            (min) |   50  |   30  |   20  |
| tI | DMACK to DIOR-/DIOW- setup (min) |    0  |    0  |    0  |
| tJ | DIOR-/DIOW- to DMACK hold  (min) |    0  |    0  |    0  |
| tS | DIOR- setup                (min) | tD-tE | tD-tE | tD-tE |
+---------------------------------------------------------------+

            Figure 7 - Single Word DMA Data Transfer





                   |<------------- t0 ------------>|                         
            _____________________________________________ _ _ _ _ _  ________
 DMARQ  ___/                                             \__________/        
                   |                               |<--->|                   
                   |                               |  tL                     
               ___________________________________________________          _
 DMACK- ______/                                                   \________/ 
              |<-->|         |                     |         |               
                tI |<-- tD ->|<------- tK -------->|         |<-->|          
                   |         |                     |         | tJ |           
 DIOR-             |_________|                     |_________     |           
 DIOW-  ___________/         \_____________________/         \_______________
                   |         |                                    |                 
                   |<--->|   |                                 -->|  |<-tZ          
 READ                 tE  ________ _ _ _ _ _ _ _ _ _ _ _  ___________          
 DD0-15 -----------------<________X_X_X_X_X_X_X_X_X_X_X_X<_______X_X_>-------
                             |    |                                
                             |<-->|                          
                             | tF                             
 WRITE                 ____________  _ _ _ _ _ _ _ _ _ ____________          
 DD0-15 --------------<____________XX_X_X_X_X_X_X_X_X_X____________>---------
                      |<---->|<--->|                                  
                        tG    tH                                            

                                                                            

      +----------------------------------------+-----------+
      | Multiword DMA              |   Mode 0  |   Mode 1  |
      | timing parameters          |    nsec   |    nsec   |
      |                            | Min | Max | Min | Max |
+-----+----------------------------+-----+-----|-----+-----|
| t0  | Cycle time                 | 480 |     | 150 |     |
| tC  | DMACK to DMREQ delay       |     | --- |     | --- |
| tD  | DIOR-/DIOW-      16-bit    | 215 |     |  80 |     |
| tE  | DIOR- data access          |     | 150 |     |  60 |
| tF  | DIOR- data hold            |   5 |     |   5 |     |
| tFZ | DIOR- to tristate (1)      |     |  20 |     |  25 |
| tG  | DIOW- data setup           | 100 |     |  30 |     |
| tH  | DIOW- data hold            |  20 |     |  15 |     |
| tI  | DMACK to DIOR-/DIOW- setup |   0 |     |   0 |     |
| tJ  | DIOR-/DIOW- to DMACK hold  |  20 |     |   5 |     |
| tKr | DIOR- negated pulse width  |  50 |     |  50 |     |
| tKw | DIOW- negated pulse width  | 215 |     |  50 |     |
| tLr | DIOR- to DMREQ delay       |     | 120 |     |  40 |
| tLw | DIOW- to DMREQ delay       |     |  40 |     |  40 |
+----------------------------------------------+-----------+

          Multiword DMA Data Transfer




Note:  Under the certain conditions the information reported by the 
drive may be incorrect.  If so, I issue a warning at the end of the report.



